With the rapid development of the semiconductor manufacturing technology, to obtain semiconductor devices with faster speed, larger storage capacity, and more functions, higher component density and higher degree of integration are the development trend of semiconductor devices. Thus, gate structures of complementary metal oxide semiconductor (CMOS) transistors may become thinner and shorter. To maintain a good electrical performance while reducing feature size, the semiconductor device's carrier mobility may need to be controlled.
One technique for controlling the carrier mobility is to control the stress in the transistor's channels. For example, by properly controlling the stress, carrier (e.g., electrons for N-type transistors, holes for N-type transistor) mobility may increase, thus, the driving current of the transistors may also increase. That is, by using a proper stress, the transistors' performance may increase significantly.
More specifically, in a stress liner technique, a tensile stress liner may be formed on NMOS transistors, and a compressive stress liner may be formed on PMOS transistors. Thus, the driving current of the PMOS transistors and the NMOS transistors may increase. Accordingly, the response speed of the electrical circuit that using the NMOS transistors and/or PMOS transistors may increase. Based on certain studies, by using a double stress liner technique, an integrated circuit may have 24% increase in its performance.
Further, silicon and germanium have the same “diamond” crystal structure. At room temperature, the lattice constant of the germanium may be larger than the silicon. Thus, by forming a silicon germanium (SiGe) layer at the source regions and drain regions of the PMOS transistors, crystal mismatch between the silicon and the SiGe may generate a compressive stress. Thereby, the performance of the PMOS transistors may increase. Accordingly, by forming a silicon carbide (SiC) layer at the source regions and drain regions of the NMOS transistors, crystal mismatch between the silicon and the SiC may generate a tensile stress. Thus, the performance of the NMOS transistors may increase.
Current techniques for forming the SiGe source/drain regions and the SiC source/drain regions may include forming certain gate structures on a semiconductor substrate; forming trenches by etching the semiconductor substrate located on the two sides of the gate structures; and forming the SiGe layer or the SiC layer at the bottom of the trenches by a selective epitaxy process. Further, during the selective epitaxy process, certain deposition gases and certain etching gases may be supplied at the same time. Thus, the SiC layer or the SiGe layer may be selectively formed at the bottom of the trenches.
Moreover, certain subsequent metal silicide process may consume the silicon in the source/drain regions, and may influence the stress at the source/drain regions. To avoid this influence, the surface of the source/drain regions that are formed by the selective epitaxy process may need to be higher than the surface of the semiconductor substrate. This type of source/drain regions is known as the elevated source/drain regions.
However, the elevated source/drain regions formed by current techniques may still have certain defects. The disclosed methods are directed to solve one or more problems set forth above and other problems.